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| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2022-10-28 15:03:47 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-10-28 12:58:19 +0100 |
| commit | 107d170dc46e14cfa575d1b995107ef2f2e51dfe (patch) | |
| tree | 19f93bd69dac774e82856a64d259a3db50ffe4c6 /scripts/gdb/linux/modules.py | |
| parent | ce992ff38e1ed495be202c22d065b42c942e0475 (diff) | |
ASoC: fsl_xcvr: Add Counter registers
These counter registers are part of register list,
add them to complete the register map
- DMAC counter control registers
- Data path Timestamp counter register
- Data path bit counter register
- Data path bit count timestamp register
- Data path bit read timestamp register
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1666940627-7611-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions