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author | Conor Dooley <conor.dooley@microchip.com> | 2023-06-07 21:28:27 +0100 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-21 07:45:15 -0700 |
commit | 069b0d51707721d5ab2001df866b66b82e4c1c35 (patch) | |
tree | 90a1f48a467c858ce8b0ba66d469efa3c8f5773f /scripts/gdb/linux/modules.py | |
parent | 2ac874343749b76e069cff5fea09c49e0bd365a0 (diff) |
RISC-V: validate riscv,isa at boot, not during ISA string parsing
Since riscv_fill_hwcap() now only iterates over possible cpus, the
basic validation of whether riscv,isa contains "rv<width>" can be moved
to riscv_early_of_processor_hartid().
Further, "ima" support is required by the kernel, so reject any CPU not
fitting the bill.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-guts-blurry-67e711acf328@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions