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authorMika Kuoppala <[email protected]>2015-08-06 17:09:17 +0300
committerDaniel Vetter <[email protected]>2015-08-14 17:50:40 +0200
commit031a8936dc660e7ae2485eb7493eba1876cf25fe (patch)
tree196c1be4c9261f6371d9917a23f402b7d3d1b687 /scripts/gdb/linux/modules.py
parent500ea70d503ed9ba448611049a4a718c2761a5f2 (diff)
drm/i915: Check idle to active before processing CSQ
If idle to active bit is set, the rest of the fields in CSQ are not valid. Bail out early if this is the case in order to prevent rest of the loop inspecting stale values. This was found by Bspec/code inspection. Doesn't seem to fix any of the known issues. Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Arun Siluvery <[email protected]> [danvet: Add note about how this was found.] Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
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