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authorConor Dooley <[email protected]>2022-08-10 09:59:15 +0100
committerConor Dooley <[email protected]>2022-08-15 21:07:41 +0100
commit7eac0081a8e958106ed3aea402c8105f30fad6d9 (patch)
tree3c3f672a16c6357efee8c61e0e50005d3ae2a0e4 /scripts/gdb/linux/mm.py
parent69dac8e431af26173ca0a1ebc87054e01c585bcc (diff)
riscv: dts: microchip: add qspi compatible fallback
The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 of the FPGA IP core. The original binding had no fallback etc, so this device tree is valid as is. There was also no functional driver for the QSPI IP, so no device with a devicetree from a previous mainline release will regress. Link: https://lore.kernel.org/linux-spi/[email protected]/ Signed-off-by: Conor Dooley <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]>
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