diff options
| author | Zumeng Chen <[email protected]> | 2016-11-28 21:55:00 +0800 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2016-11-29 20:33:55 -0500 |
| commit | ffac0e967f20b7637936dbaa21df08c55f672604 (patch) | |
| tree | 0b79a616d557f4646a717cebc75911a3803670bf /scripts/gdb/linux/lists.py | |
| parent | a0b44eea372b449ef9744fb1d90491cc063289b8 (diff) | |
net: macb: ensure ordering write to re-enable RX smoothly
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:
<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>
There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.
Signed-off-by: Zumeng Chen <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions