diff options
| author | Amelie Delaunay <[email protected]> | 2020-11-20 15:33:19 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2020-12-11 21:13:08 +0530 |
| commit | e0ebdbdcb42a66f49b7587dc50cc6f528ec55cad (patch) | |
| tree | 579c34397afd3f4551462f47fab13e66e0824186 /scripts/gdb/linux/lists.py | |
| parent | 5d4d4dfbda18063231a95dea28fdeab148f23301 (diff) | |
dmaengine: stm32-dma: take address into account when computing max width
DMA_SxPAR or DMA_SxM0AR/M1AR registers have to be aligned on PSIZE or MSIZE
respectively. This means that bus width needs to be forced to 1 byte when
computed width is not aligned with address.
Signed-off-by: Amelie Delaunay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions