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| author | Jisheng Zhang <jszhang@kernel.org> | 2023-10-06 20:14:48 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-10-07 14:17:12 +0100 |
| commit | c3dffa879ccad5f0b08deedc2c428f4f7ae7f8e6 (patch) | |
| tree | e7a53c21d246b9d921660ec4d989317e01f77658 /scripts/gdb/linux/lists.py | |
| parent | 32ecb28b8e60f75e45790fd9948470a911b0ef7d (diff) | |
riscv: dts: sophgo: add initial CV1800B SoC device tree
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions