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authorRob Herring (Arm) <[email protected]>2024-07-31 10:51:19 -0600
committerWill Deacon <[email protected]>2024-08-16 13:09:12 +0100
commita4a6e2078d85a9d94bcc7eab77845cb8cd39f680 (patch)
tree884ba4a594cf575a0ca30b99be2f8a94d60ad884 /scripts/gdb/linux/lists.py
parentbf5ffc8c80e0cf5205849cd0c9c3cb261d2beee6 (diff)
perf: arm_pmuv3: Prepare for more than 32 counters
Various PMUv3 registers which are a mask of counters are 64-bit registers, but the accessor functions take a u32. This has been fine as the upper 32-bits have been RES0 as there has been a maximum of 32 counters prior to Armv9.4/8.9. With Armv9.4/8.9, a 33rd counter is added. Update the accessor functions to use a u64 instead. Acked-by: Mark Rutland <[email protected]> Signed-off-by: Rob Herring (Arm) <[email protected]> Tested-by: James Clark <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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