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authorChris Morgan <[email protected]>2023-03-27 10:35:47 -0500
committerHeiko Stuebner <[email protected]>2023-03-30 13:27:33 +0200
commit87891399d9883ed823ba58c2be3ac20cc499ad7d (patch)
treeaedcd94e4f7fa050aad77d82f0dbc5a03007c631 /scripts/gdb/linux/lists.py
parentb37115b6534c4027df75854a44b485596d368171 (diff)
arm64: dts: rockchip: Add clk_rtc_32k to Anbernic xx3 Devices
For the Anbernic devices to display properly, we need to specify the clock frequency of the PLL_VPLL. Adding the parent clock in the rk356x.dtsi requires us to update our clock definitions to accomplish this. Fixes: 64b69474edf3 ("arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x") Signed-off-by: Chris Morgan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
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