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author | Serge Semin <[email protected]> | 2020-05-26 15:59:23 +0300 |
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committer | Arnd Bergmann <[email protected]> | 2020-05-28 13:59:56 +0200 |
commit | 78c43a059a718c1ef12f6bb826d2e39a6d22024e (patch) | |
tree | f51d63e67e852cb8364d96fc3e7ef727a82ebbfb /scripts/gdb/linux/genpd.py | |
parent | 0e698dfa282211e414076f9dc7e83c1c288314fd (diff) |
dt-bindings: bus: Add Baikal-T1 AXI-bus binding
AXI3-bus is the main communication bus connecting all high-speed
peripheral IP-cores with RAM controller and with MIPS P5600 cores on
Baikal-T1 SoC. This binding describes the DW AMBA 3 AXI Inteconnect
and Errors Handler Block synthesized on top of it, which are
responsible for the AXI-bus traffic arbitration and errors reporting
upstream to CPU. Baikal-T1 AXI-bus DT node is supposed to be compatible
with "be,bt1-axi" and "simple-bus" drivers, should have reg property with
AXI-bus QOS registers space, syscon phandle reference to the Baikal-T1
System Controller, IRQ line declared, AXI Interconnect reference clock and
reset line.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Serge Semin <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Cc: Alexey Malahov <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Olof Johansson <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/genpd.py')
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