dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding

There is a single register provided by the SoC system controller,
which can be used to tune the L2-cache RAM up. It only provides a way
to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl"
compatible string the device node can be optionally equipped with the
properties of Tag/Data/WS latencies.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Serge Semin <[email protected]>
Cc: Alexey Malahov <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Olof Johansson <[email protected]>
Cc: [email protected]
Cc: [email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

0 files changed, 0 insertions, 0 deletions