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authorBiju Das <[email protected]>2021-11-12 18:44:12 +0000
committerDaniel Lezcano <[email protected]>2021-12-09 14:05:20 +0100
commit3a3e9f23c2cae907677a236fa547610ca747e6fb (patch)
tree1a43b307200f82c7dceb0699b9f71d61d3fb4989 /scripts/gdb/linux/dmesg.py
parent92d06a3f67ad809649d26aa7698e4d42362585a8 (diff)
clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM support
RZ/G2L SoC has Generic Timer Module(a.k.a OSTM) which needs to deassert the reset line before accessing any registers. This patch adds an entry point for RZ/G2L so that we can deassert the reset line in probe callback. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daniel Lezcano <[email protected]>
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