diff options
| author | Stefan Binding <[email protected]> | 2023-01-27 16:51:11 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2023-01-31 12:10:52 +0000 |
| commit | 16838bfbf6e70b7a3381ab302248bd18c085aba5 (patch) | |
| tree | c02ea2761058f5fa13b59c60378c5f75d250a173 /scripts/gdb/linux/dmesg.py | |
| parent | e0bd53a4d1d5afa7d3a3bf46e2f0ec7940f94710 (diff) | |
ASoC: cs42l42: Wait for debounce interval after resume
Since clock stop causes bus reset on Intel controllers, we need
to wait for the debounce interval on resume, to ensure all the
interrupt status registers are set correctly.
Signed-off-by: Stefan Binding <[email protected]>
Reviewed-by: Pierre-Louis Bossart <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/dmesg.py')
0 files changed, 0 insertions, 0 deletions