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authorAlban Bedel <[email protected]>2015-04-19 14:30:02 +0200
committerRalf Baechle <[email protected]>2015-06-21 21:53:49 +0200
commit626a0695a6d98338063c528d113d9ee4ba00cd78 (patch)
tree03c999ddbda06315325bb635736c77ecb30c9539 /scripts/gdb/linux/cpus.py
parentda628e8b8b824b15c75fbc6b3defed2ff38475fe (diff)
MIPS: ath79: Correctly name the defines for the PLL_FB register
This register is named PLL_FB and is not a divider but a multiplier. To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and ARxxxx_PLL_FB_MASK. Signed-off-by: Alban Bedel <[email protected]> Cc: [email protected] Cc: Andrew Bresticker <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Wolfram Sang <[email protected]> Cc: Sergey Ryazanov <[email protected]> Cc: Gabor Juhos <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9772/ Signed-off-by: Ralf Baechle <[email protected]>
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