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| author | Stephen Boyd <sboyd@kernel.org> | 2022-02-17 11:58:37 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-02-17 11:58:37 -0800 |
| commit | 80a6359f1c9b9ef7d9409c06cafc7dac39d2d10a (patch) | |
| tree | a90d6bd381ba4a19c2e448c31010cc70b02b94d8 /scripts/gdb/linux/config.py | |
| parent | e783362eb54cd99b2cac8b3a9aeac942e6f6ac07 (diff) | |
| parent | a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd (diff) | |
Merge tag 'renesas-clk-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
- Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
- Add CAN-FD clocks on Renesas R-Car V3U
- Add support for the new Renesas RZ/V2L SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
dt-bindings: clock: renesas: Document RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
clk: renesas: r8a779a0: Add CANFD module clock
clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
clk: renesas: r8a7799[05]: Add MLP clocks
clk: renesas: r8a779f0: Add SYS-DMAC clocks
Diffstat (limited to 'scripts/gdb/linux/config.py')
0 files changed, 0 insertions, 0 deletions