drm/amd/display: Fix detection of 4 lane for DPALT

[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane

Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Solomon Chiu <[email protected]>
Signed-off-by: Hansen <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]

0 files changed, 0 insertions, 0 deletions