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authorJörg Krause <[email protected]>2018-02-05 21:47:59 +0100
committerShawn Guo <[email protected]>2018-02-12 21:13:21 +0800
commit0a929d9784ffb6f3a9d73ab59d9e3a9b10e2f719 (patch)
tree82aef20665eb5dbf74f78fa60203cfc4cd072643 /scripts/gdb/linux/config.py
parent7d77b8505aa941f326fc2df519f15437f0b0a85b (diff)
ARM: dts: imx6ul: rename mux mode name REF_CLK_32K to OSC32K_32K_OUT
This is a rebased version of patch [0]. The 32 kHz reference clock on the i.MX6UL(L) can be output by setting the external signal XTALOSC_REF_CLK_32K in one of the following ways [1]: |----------------------------------------------------------| | Signal | Pad | Mode | Direction | |----------------------------------------------------------| | XTALOSC_REF_CLK_32K | ENET1_RX_EN | ALT2 | O | | | GPIO1_IO03 | ALT3 | | | | JTAG_TCK | ALT6 | | |----------------------------------------------------------| Before patch [2] the mux mode for the external reference clock was missing. The patch named the mux mode as used in the NXP Linux 4.9.11_1.0.0 release, but the Reference Manual uses the name OSC32K_32K_OUT, e.g. in [3]. As Philipp and Shawn suggest the name from the RM should be used instead. [0] https://patchwork.kernel.org/patch/10172187/ [1] IMX6ULRM, Rev. 1, 04/2016, Table 58-1, p. 3649 [2] https://patchwork.kernel.org/patch/10156121/ [3] IMX6ULRM, Rev. 1, 04/2016, 30.5.47 SW_MUX_CTL_PAD_ENET1_RX_EN SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN), p. 1357 Signed-off-by: Jörg Krause <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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