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authorSven Peter <[email protected]>2022-09-16 11:41:51 +0200
committerJoerg Roedel <[email protected]>2022-09-26 13:49:40 +0200
commitdc09fe1c5edd9c27a52cb6dc5a7bb4452d45c71c (patch)
tree07a0ab89382e6d199cf9cc71ad944332602aa98c /scripts/gdb/linux/clk.py
parentd8fe365a4f1c1aa5e2da3e41f50a08c9bd8d6112 (diff)
iommu/io-pgtable-dart: Add DART PTE support for t6000
The DARTs present in the M1 Pro/Max/Ultra SoC use a diffent PTE format. They support a 42bit physical address space by shifting the paddr and extending its mask inside the PTE. They also come with mandatory sub-page protection now which we just configure to always allow access to the entire page. This feature is already present but optional on the previous DARTs which allows to unconditionally configure it. Signed-off-by: Sven Peter <[email protected]> Co-developed-by: Janne Grunau <[email protected]> Signed-off-by: Janne Grunau <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Hector Martin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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