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author | Shaokun Zhang <[email protected]> | 2020-06-05 17:43:41 +0800 |
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committer | Will Deacon <[email protected]> | 2020-06-08 15:46:41 +0100 |
commit | 961abd78adcb4c72c343fcd9f9dc5e2ebbe9b448 (patch) | |
tree | 9023071443732d0e82847ccac71b77eb16f21617 /scripts/gdb/linux/clk.py | |
parent | 91970bef48d68d06b2bb3f464b572ad50941f6a9 (diff) |
drivers/perf: hisi: Fix wrong value for all counters enable
In L3C uncore PMU drivers, bit16 is used to control all counters enable &
disable. Wrong value is given in the driver and its default value is 1'b1,
it can work because each PMU counter has its own control bits too.
Let's fix the wrong value.
Fixes: 2940bc433370 ("perf: hisi: Add support for HiSilicon SoC L3C PMU driver")
Signed-off-by: Shaokun Zhang <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Mark Rutland <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/clk.py')
0 files changed, 0 insertions, 0 deletions