diff options
| author | Bill Huang <[email protected]> | 2015-06-18 17:28:30 -0400 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2015-12-17 13:37:53 +0100 |
| commit | b5512b45d5ed699de328e17cd7c7027d89461920 (patch) | |
| tree | fbb0e8547493c65828b45fa0d80df76ee1669517 /scripts/gcc-plugins | |
| parent | 6929715cf6b944d8f88beb2aa25658084de106ab (diff) | |
clk: tegra: pll: Adjust vco_min if SDM present
This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid <[email protected]>
Signed-off-by: Bill Huang <[email protected]>
Signed-off-by: Rhyland Klein <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins')
0 files changed, 0 insertions, 0 deletions