mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g

The Micron mt25qu02g supports both x2 and x4 transactions. Add the
SPI_NOR_DUAL_READ flag to its spi_nor_ids[] table entry.

Tested on Pensando SoC hardware with a cadence quadspi controller
via drivers/spi/spi-cadence-quadspi.c, in x2 mode at 50MHz.
  - random data write, erase, read   - verified erase operations
  - random data write, read/compare  - verified write/read operations

Signed-off-by: David Clear <[email protected]>
Acked-by: Shannon Nelson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Tudor Ambarus <[email protected]>

0 files changed, 0 insertions, 0 deletions