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| author | Peter Griffin <[email protected]> | 2024-04-26 13:20:04 +0100 |
|---|---|---|
| committer | Martin K. Petersen <[email protected]> | 2024-05-06 21:34:37 -0400 |
| commit | d11e0a318df84f2542316ec8cc0fa4034240ee66 (patch) | |
| tree | 6d77c046ab6199ae15f6db4d4310b8469c54e924 /scripts/gcc-plugins/randomize_layout_plugin.c | |
| parent | 6f9f0d564b0411f8d86d73c7cb6b2703839e8a96 (diff) | |
scsi: ufs: exynos: Add support for Tensor gs101 SoC
Add a dedicated compatible and drv_data with associated hooks for gs101 SoC
found on Pixel 6.
Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
option, to skip initialisation of UFSPR registers as these are only
accessible via SMC call.
EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
source. This has been done so as not to effect any existing platforms.
DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs so
these register offsets now come from uic_attr struct.
Signed-off-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Will McVicker <[email protected]>
Signed-off-by: Martin K. Petersen <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/randomize_layout_plugin.c')
0 files changed, 0 insertions, 0 deletions