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author | Andre Przywara <[email protected]> | 2020-03-24 13:23:46 +0000 |
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committer | David S. Miller <[email protected]> | 2020-03-24 16:33:05 -0700 |
commit | f735c40ed93ccaeb52d026def47ac1a423df7133 (patch) | |
tree | e0610802bfd95e433f3c742261d4acdd6b5a7a0a /scripts/gcc-plugins/cyc_complexity_plugin.c | |
parent | 4e958f33ee8f404787711416fe0f78cce2b2f4e2 (diff) |
net: axienet: Autodetect 64-bit DMA capability
When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.
To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.
The actual DMA mask stays at 32-bit for now. To help bisecting, a
separate patch will enable allocations from higher addresses.
Signed-off-by: Andre Przywara <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/cyc_complexity_plugin.c')
0 files changed, 0 insertions, 0 deletions