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| author | Niklas Cassel <[email protected]> | 2019-08-30 12:29:15 +0200 |
|---|---|---|
| committer | Viresh Kumar <[email protected]> | 2019-09-03 07:53:19 +0530 |
| commit | f6081a73091c0902efb45f47706d35284ebb4e9a (patch) | |
| tree | 7024457217db3dcfb82379842f395f2c7e6ef5da /scripts/gcc-plugins/cyc_complexity_plugin.c | |
| parent | a409906003a2b5418e6e60ac2524948ea80819f2 (diff) | |
dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain
Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).
Signed-off-by: Niklas Cassel <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/cyc_complexity_plugin.c')
0 files changed, 0 insertions, 0 deletions