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| author | Krishna Yarlagadda <[email protected]> | 2019-09-04 10:13:06 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2019-09-05 10:00:05 +0200 |
| commit | d781ec21bae6ff8f9e07682e8947a654484611f5 (patch) | |
| tree | c7403f1b109700354d0d6205a712ad5393bf76ee /scripts/gcc-plugins/cyc_complexity_plugin.c | |
| parent | f04a3cc8d4550463e0c15be59d91177a5def1ca5 (diff) | |
serial: tegra: report clk rate errors
Standard UART controllers support +/-4% baud rate error tolerance.
Tegra186 only supports 0% to +4% error tolerance whereas other Tegra
chips support standard +/-4% rate. Add chip data for knowing error
tolerance level for each soc. Creating new compatible for Tegra194
chip as it supports baud rate error tolerance of -2 to +2%, different
from older chips.
Signed-off-by: Shardar Shariff Md <[email protected]>
Signed-off-by: Krishna Yarlagadda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/cyc_complexity_plugin.c')
0 files changed, 0 insertions, 0 deletions