arm64: cacheinfo: Update cache_line_size detected from DT or PPTT

cache_line_size is derived from CTR_EL0.CWG field and is called mostly
for I/O device drivers. For some platforms like the HiSilicon Kunpeng920
server SoC, cache line sizes are different between L1/2 cache and L3
cache while L1 cache line size is 64-byte and L3 is 128-byte, but
CTR_EL0.CWG is misreporting using L1 cache line size.

We shall correct the right value which is important for I/O performance.
Let's update the cache line size if it is detected from DT or PPTT
information.

Cc: Will Deacon <[email protected]>
Cc: Jeremy Linton <[email protected]>
Cc: Zhenfa Qiu <[email protected]>
Reported-by: Zhenfa Qiu <[email protected]>
Suggested-by: Catalin Marinas <[email protected]>
Reviewed-by: Sudeep Holla <[email protected]>
Signed-off-by: Shaokun Zhang <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>

0 files changed, 0 insertions, 0 deletions