diff options
| author | Biao Huang <[email protected]> | 2019-05-24 14:26:08 +0800 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2019-05-25 11:02:31 -0700 |
| commit | 5e7f7fc538d894b2d9aa41876b8dcf35f5fe11e6 (patch) | |
| tree | 9b05f3100a9355e57ce02e1f94ee73e8a65a314d /scripts/gcc-plugins/cyc_complexity_plugin.c | |
| parent | 4523a5611526709ec9b4e2574f1bb7818212651e (diff) | |
net: stmmac: fix csr_clk can't be zero issue
The specific clk_csr value can be zero, and
stmmac_clk is necessary for MDC clock which can be set dynamically.
So, change the condition from plat->clk_csr to plat->stmmac_clk to
fix clk_csr can't be zero issue.
Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input")
Signed-off-by: Biao Huang <[email protected]>
Acked-by: Alexandre TORGUE <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/cyc_complexity_plugin.c')
0 files changed, 0 insertions, 0 deletions