diff options
| author | Chao Peng <[email protected]> | 2018-10-24 16:05:12 +0800 |
|---|---|---|
| committer | Paolo Bonzini <[email protected]> | 2018-12-21 11:28:35 +0100 |
| commit | 2ef444f1600bfc2d8522df0f537aafef79befa7e (patch) | |
| tree | 1bdc097495a69ed493a21ef07cb07e77db0da902 /scripts/gcc-plugins/cyc_complexity_plugin.c | |
| parent | 86f5201df0d3e3efc78d3eac7fc5a59b813287cd (diff) | |
KVM: x86: Add Intel PT context switch for each vcpu
Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.
Signed-off-by: Chao Peng <[email protected]>
Signed-off-by: Luwei Kang <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/cyc_complexity_plugin.c')
0 files changed, 0 insertions, 0 deletions