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| author | Imre Deak <imre.deak@intel.com> | 2021-08-02 22:01:48 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-08-03 16:43:55 +0300 |
| commit | 233624e0d5a0854638eff9e77fc37161890e9440 (patch) | |
| tree | ee2a237dfed25ba87ac1c7c84992a0b0e64421fc /scripts/gcc-plugins/cyc_complexity_plugin.c | |
| parent | 82929a2140eb99f1f1d21855f3f580e70d7abdd8 (diff) | |
drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
CI test results/further experiments show that the workaround added in
commit 573d7ce4f69a ("drm/i915/adlp: Add workaround to disable CMTG clock gating")
can be applied only while DPLL0 is enabled. If it's disabled the
TRANS_CMTG_CHICKEN register is not accessible. Accordingly move the WA
to DPLL0 HW state sanitization and enabling.
This fixes an issue where the WA won't get applied (and a WARN is thrown
due to an unexpected value in TRANS_CMTG_CHICKEN) if the driver is
loaded without DPLL0 being enabled: booting without BIOS enabling an
output with this PLL, or reloading the driver.
While at it also add a debug print for the unexpected register value.
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210802190148.2099625-1-imre.deak@intel.com
Diffstat (limited to 'scripts/gcc-plugins/cyc_complexity_plugin.c')
0 files changed, 0 insertions, 0 deletions