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| author | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-10 15:44:30 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-24 16:55:45 -0500 |
| commit | d30fea25845ff65ea1fb255d7b615cd02b65095b (patch) | |
| tree | ff4f00e7f1393d7bdb0421a0290b18f0635323b2 /scripts/clang-tools/gen_compile_commands.py | |
| parent | 04e82fa5951ca66495d7b05665eff673aa3852b4 (diff) | |
PCI/ATS: Show PASID Capability register width in bitmasks
The PASID Capability and Control registers are both 16 bits wide. Use
16-bit wide constants in field names to match the register width. No
functional change intended.
Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Diffstat (limited to 'scripts/clang-tools/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions