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| author | Ilpo Järvinen <[email protected]> | 2024-02-06 15:57:14 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2024-03-08 15:22:46 -0600 |
| commit | a37e12bcab22efa05802f87baa0692365ae0ab4d (patch) | |
| tree | 71428563172d75bc5cfe568c824edb4291fbaed7 /scripts/clang-tools/gen_compile_commands.py | |
| parent | 002bf2fbc00e5c4b95fb167287e2ae7d1973281e (diff) | |
PCI/AER: Use explicit register size for PCI_ERR_CAP
Use u32 for PCIe AER Capability register variable and name it "aercc"
(Advanced Error Capabilities and Control register, PCIe r6.1 sec 7.8.4.7)
instead of "temp".
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ilpo Järvinen <[email protected]>
[bhelgaas: make subject more specific and match similar previous patches]
Signed-off-by: Bjorn Helgaas <[email protected]>
Diffstat (limited to 'scripts/clang-tools/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions