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authorHugo Villeneuve <[email protected]>2023-08-07 17:45:55 -0400
committerGreg Kroah-Hartman <[email protected]>2023-08-22 15:30:00 +0200
commit9baeea723c0fb9c3ba9a336369f758ed9bc6831d (patch)
tree3651e22276afe52000f872e44718ca7d360416a3 /scripts/clang-tools/gen_compile_commands.py
parent0499942928341d572a42199580433c2b0725211e (diff)
serial: sc16is7xx: fix bug when first setting GPIO direction
When configuring a pin as an output pin with a value of logic 0, we end up as having a value of logic 1 on the output pin. Setting a logic 0 a second time (or more) after that will correctly output a logic 0 on the output pin. By default, all GPIO pins are configured as inputs. When we enter sc16is7xx_gpio_direction_output() for the first time, we first set the desired value in IOSTATE, and then we configure the pin as an output. The datasheet states that writing to IOSTATE register will trigger a transfer of the value to the I/O pin configured as output, so if the pin is configured as an input, nothing will be transferred. Therefore, set the direction first in IODIR, and then set the desired value in IOSTATE. This is what is done in NXP application note AN10587. Fixes: dfeae619d781 ("serial: sc16is7xx") Cc: [email protected] Signed-off-by: Hugo Villeneuve <[email protected]> Reviewed-by: Lech Perczak <[email protected]> Tested-by: Lech Perczak <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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