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authorGreentime Hu <[email protected]>2023-06-05 11:07:05 +0000
committerPalmer Dabbelt <[email protected]>2023-06-08 07:16:41 -0700
commit7017858eb2d7ed7a295be02c71124049a6409295 (patch)
treee403b59432c0d41755b46320fc570dfe4ac67e9d /scripts/clang-tools/gen_compile_commands.py
parent0a3381a01dcc3d0537732794c007f32e4dfd1efc (diff)
riscv: Introduce riscv_v_vsize to record size of Vector context
This patch is used to detect the size of CPU vector registers and use riscv_v_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. If a core detects VLENB that is different from the boot core, then it warns and turns off V support for user space. Co-developed-by: Guo Ren <[email protected]> Signed-off-by: Guo Ren <[email protected]> Co-developed-by: Vincent Chen <[email protected]> Signed-off-by: Vincent Chen <[email protected]> Signed-off-by: Greentime Hu <[email protected]> Signed-off-by: Andy Chiu <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Reviewed-by: Palmer Dabbelt <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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