diff options
| author | Sugar Zhang <[email protected]> | 2021-08-26 12:01:48 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-08-26 13:59:31 +0100 |
| commit | 6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af (patch) | |
| tree | e456bf342072a723076a8b77880a3c2281fbd217 /scripts/clang-tools/gen_compile_commands.py | |
| parent | ebfea67125767a779af63ae6de176709713c8826 (diff) | |
ASoC: rockchip: i2s: Fixup clk div error
MCLK maybe not precise as required because of PLL,
but which still can be used and no side effect. so,
using DIV_ROUND_CLOSEST instead div.
e.g.
set mclk to 11289600 Hz, but get 11289598 Hz.
Signed-off-by: Sugar Zhang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/clang-tools/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions