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| author | Sam Protsenko <[email protected]> | 2023-08-18 22:17:26 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2023-08-22 14:47:22 +0200 |
| commit | 592d7a4663d2f23eda360048e7a35149cc3aa8d5 (patch) | |
| tree | 7f42a237da1815ff82c97d7c75c1c1e251666fd4 /scripts/clang-tools/gen_compile_commands.py | |
| parent | 52ecf812de2548ea0704e67f99cea1d0f3b8b173 (diff) | |
usb: dwc3: exynos: Add support for Exynos850 variant
Add Exynos850 compatible string and associated driver data. Only two
clocks are needed for this SoC:
- bus_early: bus clock needed for registers access
- ref: USB 2.0 DRD reference clock (50 MHz)
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'scripts/clang-tools/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions