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author | Adam Ford <aford173@gmail.com> | 2023-05-11 20:04:23 -0500 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2023-05-15 11:15:31 +0800 |
commit | 07bb2e368820a4de9b4b586691e143976b74ea44 (patch) | |
tree | 702cfeebdf832a002710a78b419fdd81d2580ad7 /scripts/clang-tools/gen_compile_commands.py | |
parent | 91aa4b3782448a7a13baa8cbcdfd5fd19defcbd9 (diff) |
arm64: dts: imx8mp: Fix video clock parents
There are a few clocks whose parents are set in mipi_dsi
and lcdif nodes, but these clocks are used by the media_blk_ctrl
power domain. This may cause an issue when re-parenting, because
the media_blk_ctrl may start the clocks before the reparent is
done resulting in a disp_pixel clock having the wrong parent and
rate.
Fix this by moving the assigned-clock-parents and rates to the
media_blk_ctrl node to configure these clocks before they are enabled.
After this patch, both disp1_pix_root and dixp2_pix_root clock
become children of the video_pll1.
video_pll1_ref_sel 24000000
video_pll1 1039500000
video_pll1_bypass 1039500000
video_pll1_out 1039500000
media_disp2_pix 1039500000
media_disp2_pix_root_clk 1039500000
media_disp1_pix 1039500000
media_disp1_pix_root_clk 1039500000
Fixes: eda09fe149df ("arm64: dts: imx8mp: Add display pipeline components")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/clang-tools/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions