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author | Marek Szyprowski <[email protected]> | 2019-10-25 11:34:35 +0200 |
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committer | Sylwester Nawrocki <[email protected]> | 2019-10-29 14:57:22 +0100 |
commit | 45f10dabb56bc5dee52df47dccd3bfab1e58eea1 (patch) | |
tree | 785cab6109225be5769e8d9719fa10b4a7df6e88 /scripts/checkkconfigsymbols.py | |
parent | e21be0d1d7bd7f78a77613f6bcb6965e72b22fc1 (diff) |
clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.
Suggested-by: Marian Mihailescu <[email protected]>
Signed-off-by: Marek Szyprowski <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>
Diffstat (limited to 'scripts/checkkconfigsymbols.py')
0 files changed, 0 insertions, 0 deletions