diff options
| author | Harigovindan P <harigovi@codeaurora.org> | 2020-01-07 11:10:08 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-01-07 08:26:30 -0800 |
| commit | e3ff68812384dd7f219b331535ede94b0974d5a7 (patch) | |
| tree | 9202b4023f6a6a9b06bbf10b525da045baa5c089 /scripts/bpf_helpers_doc.py | |
| parent | 6125bd327e16a451efb5a00bc4224e164d19f77e (diff) | |
drm/msm: update LANE_CTRL register value from default value
LANE_CTRL register in latest version of DSI controller (v2.2)
has additional functionality introduced to enable/disable HS
signalling with default value set to enabled. To accommodate this
change, LANE_CTRL register should be read and bit wise ORed to enable
non continuous clock mode. Without this change, if register is written
directly, HS signalling will be disabled resulting in black screen.
Changes in v1:
-Update LANE_CTRL register value
Changes in v2:
-Changing commit message accordingly.
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'scripts/bpf_helpers_doc.py')
0 files changed, 0 insertions, 0 deletions