phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init

There were some problem in ipq8074 Gen2 PCIe phy init sequence.

1. Few register values were wrongly updated in the phy init sequence.
2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter
   register which is added in serdes table causing the wrong register
   was getting updated.
3. Clocks and resets were not added in the phy init.

Fix these to make Gen2 PCIe port on ipq8074 devices to work.

Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074")
Cc: [email protected]
Co-developed-by: Selvam Sathappan Periakaruppan <[email protected]>
Signed-off-by: Selvam Sathappan Periakaruppan <[email protected]>
Signed-off-by: Sivaprakash Murugesan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>

0 files changed, 0 insertions, 0 deletions