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| author | Roger Quadros <[email protected]> | 2022-06-28 15:22:55 +0300 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2022-08-30 10:42:58 +0530 |
| commit | 86d11e225e3fd204d42346effba08a7c465f6a57 (patch) | |
| tree | dc81dbf07f8acda3f18e1dae4f7ce315eef588e3 /scripts/bpf_doc.py | |
| parent | edd473d4293aa5a1684f4efe0d4e0c0318a92976 (diff) | |
phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate
For J7200-SR2.0 and AM64 we don't model Common refclock divider as
a clock divider as the divisor rate is fixed based on operating
reference clock frequency. We just program the recommended value
into the register. This simplifies the device tree and implementation
a lot.
Signed-off-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'scripts/bpf_doc.py')
0 files changed, 0 insertions, 0 deletions