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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-09-15 10:48:36 +0300 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-10-04 12:16:58 +0200 |
| commit | dbe68bc9e82b6951ff88285ccffc191d872d9a01 (patch) | |
| tree | 95ef9339fe07e79940ae1f2e4489e4b3b6118214 /samples | |
| parent | 968f6e9d51e2da6eade2afb65629ab87a8a0faf3 (diff) | |
ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate")
and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement")
the slew-rate is enabled by default for each configured pin. The datasheet
specifies at chapter "Output Driver AC Characteristics" that HSIO
drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate
setting but are rather calibrated against an external 1% resistor mounted
on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal
frequency and the external load, it is possible to adjust their target
output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled
at the moment in device tree).
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com
Diffstat (limited to 'samples')
0 files changed, 0 insertions, 0 deletions