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authorImre Deak <[email protected]>2024-04-17 01:10:00 +0300
committerImre Deak <[email protected]>2024-04-19 17:05:35 +0300
commitf1d6aec41f13aad3c3ff8daa9fddb38539afe8f6 (patch)
tree6b36cd763d21fe88f2b7fb173a1f46ba09663f10 /rust/helpers/helpers.c
parentaaba7a95ddffbf609261a8ba6c5d344b7cc6dca9 (diff)
drm/i915/dp: Fix DSC line buffer depth programming
Fix the calculation of the DSC line buffer depth. This is limited both by the source's and sink's maximum line buffer depth, but the former one was not taken into account. On all Intel platform's the source's maximum buffer depth is 13, so the overall limit is simply the minimum of the source/sink's limit, regardless of the DSC version. This leaves the DSI DSC line buffer depth calculation as-is, trusting VBT. On DSC version 1.2 for sinks reporting a maximum line buffer depth of 16 the line buffer depth was incorrectly programmed as 0, leading to a corruption in color gradients / lines on the decompressed screen image. Cc: [email protected] Reviewed-by: Ankit Nautiyal <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Acked-by: Maarten Lankhorst <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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