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authorTudor Ambarus <[email protected]>2023-03-28 10:15:16 +0000
committerNicolas Ferre <[email protected]>2023-03-30 21:20:59 +0200
commit46a8a137d8f60929923a609cdddde06e7007b0df (patch)
tree0617f766850175d0a1e484650d379b91e721b474 /rust/helpers/helpers.c
parent09ce8651229bb2d8e10ce0499e07da6f9bfaf5d8 (diff)
ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency
sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus <[email protected]> Tested-by: Nicolas Ferre <[email protected]> # on sama5d2 ICP Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Ferre <[email protected]>
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