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authorBiju Das <[email protected]>2024-08-30 21:30:03 +0100
committerKrzysztof Kozlowski <[email protected]>2024-08-31 07:30:32 +0200
commit84d1078af52f6a099267fccfb1dda602ac8b66d0 (patch)
tree3178048a2e13c00d0f4dccf9c0d7c47170fc4e02 /rust/helpers.c
parentff390189b7f2cfa20c644bc58b4462b5e2621838 (diff)
memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins
The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL SMARC EVK uses Renesas AT25QL128A flash. With current pin setting for IOVF pin, 4-bit flash write fails for AT25QL128A flash. Use Hi-Z state as the default for IOVF pin, so that spi controller driver in linux will be independent of flash type. To support this, during board production, the bit 4 of the NV config register must be cleared by the bootloader for Micron flash. Output from u-boot after clearing bit4 of NVCR register. => renesas_micron_flash_nvcr SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB NVCR=0xef Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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