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author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2024-02-16 23:44:57 +0530 |
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committer | Niklas Cassel <cassel@kernel.org> | 2024-02-19 10:44:37 +0100 |
commit | 26c8404e162b43dddcb037ba2d0cb58c0ed60aab (patch) | |
tree | f18bc1e9934d9cbc631bba5924734a395716a461 /net | |
parent | 9815e39617541ef52d0dfac4be274ad378c6dc09 (diff) |
ata: ahci_ceva: fix error handling for Xilinx GT PHY support
Platform clock and phy error resources are not cleaned up in Xilinx GT PHY
error path.
To fix introduce the function ceva_ahci_platform_enable_resources() which
is a customized version of ahci_platform_enable_resources() and inline with
SATA IP programming sequence it does:
- Assert SATA reset
- Program PS GTR phy
- Bring SATA by de-asserting the reset
- Wait for GT lane PLL to be locked
ceva_ahci_platform_enable_resources() is also used in the resume path
as the same SATA programming sequence (as in probe) should be followed.
Also cleanup the mixed usage of ahci_platform_enable_resources() and custom
implementation in the probe function as both are not required.
Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy")
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions