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authorIcenowy Zheng <[email protected]>2017-03-25 22:50:08 +0800
committerKishon Vijay Abraham I <[email protected]>2017-04-10 16:42:57 +0530
commita0b1910e857897ae6c420fa0ece52c87d7cff373 (patch)
tree81a669be7e90967455eb067dd61fa863b23c24e4 /net/unix/sysctl_net_unix.c
parent0ccf7d87fb4a9dcbb55156c846e2593fe77c206b (diff)
dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
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