diff options
| author | Kuninori Morimoto <[email protected]> | 2017-10-13 06:03:06 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2017-10-13 11:19:01 +0100 |
| commit | 6cba3fa98cdd045e020f096bb8888225d3906895 (patch) | |
| tree | 348b9a019fa1be57af73674c7b057aedab730015 /net/unix/sysctl_net_unix.c | |
| parent | 3a9fa27be507b19107a8b3fe03a67e8145aea88c (diff) | |
ASoC: rsnd: more clear ADG clock debug info
ADG inputs clock from CLK{A,B,C,I} and outputs clock from
CLKOUT{0,1,2,3} which is selected by BRG{A,B}.
Now, ADG is assuming BRGA is for 44100Hz related clocks,
BRGB is for 48000Hz related clocks.
Clock related debug is very difficult/confusable.
This patch cleanups clock related debug info.
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
0 files changed, 0 insertions, 0 deletions