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authorGeorgi Djakov <[email protected]>2017-12-05 17:46:58 +0200
committerStephen Boyd <[email protected]>2018-01-02 10:00:24 -0800
commit0c6ab1b8f8940d4ddbfff7ddff080cbfb5f32b02 (patch)
tree86310ba2d4e2a574951dffa428e33ac87972fa84 /net/unix/sysctl_net_unix.c
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
clk: qcom: Add A53 PLL support
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Tested-by: Amit Kucheria <[email protected]> [[email protected]: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
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