phy: bcm-ns-usb3: split all writes into reg & val pairs

So far all the PHY initialization was implemented using some totally
magic values. There was some pattern there but it wasn't clear what is
it about.

Thanks to the patch submitted by Broadcom:
[PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC
and the upstream "iproc-mdio" driver we now know there is a MDIO bus
underneath with PHY(s) and their registers.

It allows us to clean the driver a bit by making all these values less
magical. The next step is switching to using a proper MDIO layer.

Signed-off-by: Rafał Miłecki <[email protected]>
Acked-by: Jon Mason <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>

0 files changed, 0 insertions, 0 deletions