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authorRhyland Klein <[email protected]>2016-03-21 15:58:52 -0400
committerThierry Reding <[email protected]>2016-04-28 12:41:50 +0200
commit926655f929063619b13db8b4f2ef8c9a08605492 (patch)
treeffcb529ae83a81e7840b9f57ccf11006fb15fd56 /net/switchdev/switchdev.c
parenta91bb605ec5f93676e503267c89469d02c5b4cbc (diff)
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields. Additionally define PLL_RE_OUT1 on Tegra210. Signed-off-by: Rhyland Klein <[email protected]> [[email protected]: define PLLRE_OUT1 register offset] Signed-off-by: Thierry Reding <[email protected]>
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